SRW

Top  Previous  Next

 

The 16 - bits of accu 1-L are shifted right about the number that is specified as operand (0-15). Bits which are shifted out right get lost, from left it is refilled with zeros.

 

If no operand is specified the accu 2-LL will be used instead.

 

See also:

SLW

SLD

SRD

SSI

SSD

 

List of operations